Array substrate, manufacturing method thereof, and display device

ABSTRACT

Embodiments of the invention relate to an array substrate, a manufacturing method thereof and a display device comprising the array substrate. The array substrate comprises a gate line and a data line which define a pixel region, the pixel region comprises a thin film transistor region and an electrode pattern region, a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode and a passivation layer are formed in the thin film transistor region, the gate insulation layer, a pixel electrode, the passivation layer and a common electrode are formed in the electrode pattern region, and the common electrode and the pixel electrode form a multi-dimensional electric field. A color resin layer is formed between the gate insulation layer and the pixel electrode.

BACKGROUND

Embodiments of the invention relate to an array substrate, amanufacturing method of the array substrate and a display device.

Thin film transistor liquid crystal display (TFT-LCD) has advantages ofsmall volume, low power consumption, free of radiation and the like, andoccupies a dominant role in current panel display market. With theprogress of technology, the consumers have a higher demand on thedisplay effect of mobile products, and the display effect of a normaltwisted nematic (TN) type liquid crystal display can not meet suchdemand any more. At present, many manufacturers have applied variouswide viewing angle mode, which have a better display effect, to mobileproducts, such as in-plane switching (IPS) mode, vertical alignment (VA)mode, advanced-super dimensional switching (AD-SDS, ADS for short) modeand the like. In the ADS mode, a multi-dimensional electric field isformed with both an electric field generated at edges of slit electrodesin a same plane and an electric field generated between a slit electrodelayer and a plate-like electrode layer, so that liquid crystal moleculesat all orientations, which are located directly above the electrodes orbetween the slit electrodes in a liquid crystal cell, can be rotated, Inthis way, the work efficiency of liquid crystal can be enhanced and thelight transmittance can be increased. The ADS mode can improve the imagequality of the thin film transistor liquid crystal display and hasadvantages of high transmittance, wide viewing angle, high apertureratio, low chromatic aberration, high response speed, free of push Mura,etc.

In recent years, the application of liquid crystal display device tomobile phone, personal digital assistant (PDA), flat panel computer andthe like gradually increases, and the liquid crystal display device ismore and more applied to the outdoor mobile products. However, thenormal liquid crystal display device has a poor contrast when being usedoutdoors under the sunlight so that the readability of the screen is notgood. In contrast, the liquid crystal display device withtrans-reflective structure can increase the contrast of the displaydevice used outdoors by increasing the reflectivity of the panel, sothat the display device with trans-reflective structure can maintain anexcellent readability even when being used outdoors. Thus, the wideviewing angle trans-reflective TFT-LCD, which has an excellent displayeffect and can maintain an excellent readability outdoors, is adevelopment trend of mobile products.

FIG. 1 shows a structure of a conventional TFT array substrate in an ADSmode. The array substrate comprises a gate line and a data line whichdefine a pixel region, and the pixel region comprises a thin filmtransistor region and an electrode pattern region. A gate electrode 2, agate insulation layer 3, an active layer 4, a source electrode 5, adrain electrode 6 and a passivation layer 9 are formed in the thin filmtransistor region. The gate insulation layer 3, a pixel electrode 7, thepassivation layer 9 and a common electrode 8 are formed in the electrodepattern region. The common electrode 8 and the pixel electrode 7 form amulti-dimension electric field. This array substrate is applied to theliquid crystal display device, and the liquid crystal display devicefurther comprises a color filter substrate and a back light source inaddition to the array substrate. Generally, the array substrate and thecolor filter substrate are manufactured separately, then the arraysubstrate and the color filter substrate are bonded together by a cellassembly process to form a display panel, and finally the display deviceis formed by a module process.

However, since the TFT region having a different thickness (as shown inFIG. 1, the passivation layer 9 has an obvious protrusion at the TFT)influences the filling uniformity of the liquid crystal molecules afterthe cell assembly process, there exists an irregular arrangement of theliquid crystal molecules in the reflective region. In addition, sincethe pixel electrode is relatively close to the data line, it may beinfluenced by the voltage of the data line, which is disadvantageous tohorizontal driving of the ADS mode. In this case, light leakage mayoccur because the abnormal liquid crystal driving may cause the rotationangle of the liquid crystal molecules not sufficient. The light from theback light source may not be fully utilized in the display region due tothe light leakage, thus the contrast may be reduced, and the displayquality may be decreased.

SUMMARY

According to an embodiment of the invention, there is provided an arraysubstrate. The array substrate comprises a gate line and a data linewhich define a pixel region, the pixel region comprises a thin filmtransistor region and an electrode pattern region, a gate electrode, agate insulation layer, an active layer, a source electrode, a drainelectrode and a passivation layer are formed in the thin film transistorregion, the gate insulation layer, a pixel electrode, the passivationlayer and a common electrode are formed in the electrode pattern region,and the common electrode and the pixel electrode form amulti-dimensional electric field. A color resin layer is formed betweenthe gate insulation layer and the pixel electrode.

According to another embodiment of the invention, there is provided amethod of manufacturing an array substrate. The method comprisesprocesses of forming a pixel region, the pixel region comprises a thinfilm transistor region and an electrode pattern region, a gateelectrode, a gate insulation layer, an active layer, a source electrode,a drain electrode and a passivation layer are formed in the thin filmtransistor region, the gate insulation layer, a pixel electrode, thepassivation layer and a common electrode are formed in the electrodepattern region, and the common electrode and the pixel electrode form amulti-dimensional electric field. After forming the gate insulationlayer and before forming the pixel electrode, a color resin layer isformed above the gate insulation layer.

According to another embodiment of the invention, there is provided adisplay device. The display device comprises the above-described arraysubstrate.

According to the embodiments of the invention, since the color resinlayer is formed above the gate insulation layer, the distance betweenthe pixel electrode and the data line or the gate line is increased(that is, the interlayer thickness is increased), and thus it isadvantageous to make the pixel region to be more flat and prevent thepixel electrode from being influenced by the voltages of the data lineand the gate line. Accordingly, the irregular arrangement of the liquidcrystal molecules in the reflective region can be prevented, the ADSmode of horizontal driving can be maintained, the proper rotation of theliquid crystal molecules can be ensured, the light leakage can beavoided and the contrast can be improved.

According to the embodiments of the invention, the reflective regionpattern is formed by using the metal material for the gate electrode,and the reflective region metal electrode layer is formed by using themetal material for the source and drain electrodes, and the color resinlayer is formed on the reflective region metal electrode layer. It isalso advantageous to increase the distance between the pixel electrodeand the reflective region electrode layer, thus the light leakage causedby the irregular arrangement of the liquid crystal molecules in thereflective region can be prevented. In addition, the disposition of thereflective region (i.e. employing a trans-reflective manner) makes theliquid crystal display device to be able to enhance display effect undera strong light by using extern light, and thus the product quality canbe improved and manufacturing cost can be reduced.

According to the embodiments of the invention, since it does not need tobond the array substrate with a separate color filter substrate, theliquid crystal molecules simply is filled between the array substrateand a glass substrate, and thus the alignment difficulty can be reduced.Meanwhile, since the common electrode is connected with the bottomelectrode of the storage capacitance through a via hole in theinsulation layer, a high aperture ratio can be obtained and thetransmittance can be increased.

BRIEF DESCRIPTION OF DRAWINGS

In order to describe the technical solutions of the embodiments of theinvention, it will give a brief description to the figures of theembodiments below. Obviously, the below described figures are onlyrelate some embodiments of the invention, and not intended to restrictthe invention.

FIG. 1 is a schematic view showing a conventional array substrate in anADS mode;

FIG. 2 is a schematic view showing an array substrate according to afirst embodiment of the invention;

FIG. 3 a and FIG. 3 b are schematic views showing a method ofmanufacturing the array substrate according to the first embodiment ofthe invention; and

FIG. 4 is a schematic view showing an array substrate according to asecond embodiment of the invention.

DETAILED DESCRIPTION

In order to make aims, technical solution and advantages of theembodiments of the invention to be clearer, the technical solutions ofthe embodiments of the invention will be described below clearly andfully in connection with the figures of the embodiments of theinvention. Obviously, the described embodiments are a portion of theembodiments of the invention, not to be all embodiments. Based on thedescribed embodiments of the invention, all additional embodiments,which could be obtained by those skilled in the art without payingcreative work, belong to the scope of the protection of the invention.

First Embodiment

The present embodiment provides an array substrate, which may employ theADS mode. As shown in FIG. 2, the array substrate comprises a gate lineand a data line which define a pixel region, and the pixel regioncomprises a thin film transistor region and an electrode pattern region.A gate electrode 2, a gate insulation layer 3, an active layer 4, asource electrode 5, a drain electrode 6, and a passivation layer 9 areformed in the thin film transistor region. The gate insulation layer 3,a pixel electrode 7, the passivation layer 9 and a common electrode 8are formed in the electrode pattern region. The common electrode 8 andthe pixel electrode 7 may form a multi-dimensional electric field.Alternatively, a protection layer 12 may be formed on the gateinsulation layer 3, the source electrode 5 and the drain electrode 6,and subsequently, a black matrix layer 10 may be formed above the sourceelectrode 5, the drain electrode 6 and a TFT channel. Alternatively, theblack matrix layer 10 may be directly formed above the source electrode5, the drain electrode 6 and the TFT channel without forming theprotection layer 12.

When the protection layer 12 is formed, the black matrix layer 10 isformed on a portion of the protection layer 12 corresponding to the thinfilm transistor, and a color resin layer 11 is formed between thesurface, which is formed by the protection layer 12 and the black matrixlayer 10, and the pixel electrode 7. When the black matrix layer 10 isdirectly formed on the thin film transistor without forming theprotection layer 12, the color resin layer 11 is formed between thesurface, which is formed by the gate insulation layer 3 and the blackmatrix layer 10, and the pixel electrode 7. The protection layer 12 isadvantageous to make the pixel region to be more flat.

A storage capacitance bottom electrode 13 formed by the metal materialfor the gate electrode 2 is further provided in the electrode patternregion. An insulation layer via hole is formed above the storagecapacitance bottom electrode 13. The insulation layer via holepenetrates the passivation layer 9, the color resin layer 11, theprotection layer 12 (if is formed) and the gate insulation layer 3. Thecommon electrode 8 is connected with the storage capacitance bottomelectrode 13 by the insulation layer via hole.

In the present embodiment, the storage capacitance bottom electrode 13may be a common electrode line (Cst on common) to provide a constantvoltage to the common electrode 8, or may be a portion of the gate line(Cst on Gate).

In addition, the present embodiment further provides a method ofmanufacturing the array substrate. As shown in FIGS. 3 a and 3 b, themethod may comprise: firstly forming the gate line, the gate electrode2, the gate insulation layer 3, the active layer 4, the source electrode5, the drain electrode 6 and the data line, so as to form the thin filmtransistor region; subsequently forming the color resin layer 11; andfinally forming the pixel electrode 7, the passivation layer 9 and thecommon electrode 8, so as to form the electrode pattern region. Forexample, the method comprises the following steps:

Step S1: firstly forming the gate line, the gate electrode 2, the gateinsulation layer 3, the active layer 4, the source electrode 5, thedrain electrode 6 and the data line so as to form the thin filmtransistor region, and subsequently forming the protection layer 12 byan insulation material. The step may comprise the following steps S101,S102 and S103.

Step S101: depositing a first metal layer having conductivity on asubstrate 1, and forming the gate line, the gate electrode 2, and thestorage capacitance bottom electrode 13 in the electrode pattern regionby using a first patterning process;

Step S102: sequentially depositing the gate insulation layer 3 formed bymaterials such as SiNx, SiON and the like, and a semiconductor activelayer 4 formed by materials such as a-Si and the like on the substrateafter step S101; depositing a second metal layer having conductivity,and forming the active layer 4, the source electrode 5, the drainelectrode 6 and the data line through a second patterning process byusing a halftone mask or a gray tone mask so as to form the thin filmtransistor region;

Step S103: forming the protection layer 12 by using materials such asSiNx and the like on the substrate after step S102 to protect the pixelregion.

Step S2: depositing an opaque resin layer on the substrate after thestep S1, and forming the black matrix layer 10 at the predeterminedposition in the thin film transistor region by using a third patterningprocess.

Step S3: forming the color resin layer 11. The step comprises thefollowing steps S301 and S302:

Step S301: depositing a red resin layer R on the substrate after thestep S2 and performing a fourth patterning process, depositing a greenresin layer G and a blue resin layer B and performing a fifth patterningprocess and a sixth patterning process in a manner similar to the redresin layer R, so as to form the color resin layer 11, and etching awaythe color resin layer 11 above the storage capacitance bottom electrode13;

Step S302: etching away the gate insulation layer 3 and the protectionlayer 12 above the storage capacitance bottom electrode 13 by using aseventh patterning process, to expose the storage capacitance bottomelectrode 13 and form the insulation layer via hole opened upwardly.

In the following steps S4 and S5, the pixel electrode 7, the passivationlayer 9 and the common electrode 8 will be formed. For example, thesesteps are performed as follows

Step S4: depositing a first transparent conductive layer on thesubstrate after the step S3, and forming the pixel electrode 7 by usingan eighth patterning process;

Step S5: forming the passivation layer 9 and the common electrode 8. Thecommon electrode 8 is connected with the storage capacitance bottomelectrode 13 by the insulation layer via hole formed in the above StepS302. The step comprises the following steps S501 and S502:

Step S501: depositing a transparent resin material layer on thesubstrate after the step S4, and forming the passivation layer 9 byusing a ninth patterning process;

Step S502: depositing a second transparent conductive layer on thesubstrate after the step S501, and forming the common electrode 8 byusing a tenth patterning process.

In the above described manufacturing method, the materials for formingthe opaque resin layer preferably have a sheet resistance greater than10¹² Ω/sq, a thickness of 0.5 μm˜2 μm, and an Optical density (OP)larger than 4.

Preferably, the materials for forming the R, G, and B resin layers havea dielectric constant in the range of 3˜5 F/m and a thickness of 1 μm˜4μm.

The materials for forming the first and second transparent conductivelayers preferably have wet etch selectively in relative to the wiringmetal (for example, metal or alloy which has conductivity such as Mo,Al, Ti, Cu and so on), and for example are indium tin oxide (ITO),indium zinc oxide (IZO) and so on. These materials have a goodtransparency after a treatment of Transparent Conducting Oxide (TCO).

Preferably, the transparent resin material layer for forming thepassivation layer 9 have a dielectric constant in a range of 3˜5 F/m anda thickness of 1 μm˜4 μm.

The above opaque resin layer for forming the black matrix layer, the R,G and B resin layers, and the transparent resin material layer forforming the passivation layer may use acrylate, polyimide, epoxy resin,phenol-aldehyde resin and so on as a matrix. The opaque resin layer andthe R, G, and B resin layers are formed by adding pigment or dye ofdifferent color into the above matrix.

The Second Embodiment

The present embodiment provides another array substrate. The repetitionsof the above first embodiment will be omitted in the present embodiment,and it will give a detailed explanation below on the differences betweenthe present embodiment and the first embodiment.

The array substrate provided by the present embodiment may employ theADS mode. As shown in FIG. 4, the array substrate comprises a gate lineand a data line which define a pixel region, and the pixel regioncomprises a thin film transistor region and an electrode pattern region.A gate electrode 2, a gate insulation layer 3, an active layer 4, asource electrode 5, a drain electrode 6, and a passivation layer 9 areformed in the thin film transistor region. The gate insulation layer 3,a pixel electrode 7, the passivation layer 9 and a common electrode 8are formed in the electrode pattern region. The common electrode 8 andthe pixel electrode 7 may form a multi-dimensional electric field.

A reflective region pattern 14 formed by the metal material for the gateelectrode 2 is disposed at the position corresponding to the electrodepattern region on the substrate 1. The gate insulation layer 3 is formedon the reflective region pattern 14. A reflective region metal electrodelayer 15 formed of the metal material for the source and drainelectrodes is disposed at position corresponding to the reflectiveregion pattern 14 on the gate insulation layer 3. Thus, atrans-reflective array substrate is formed, which may be used under theenvironment of strong light such as outdoors.

In addition, the present embodiment also provides a method ofmanufacturing the array substrate. The method comprises the followingsteps.

Step 1: forming the gate line, the gate electrode 2 and the storagecapacitance bottom electrode (not shown) by using a first metalmaterial, and remaining a portion of the first metal material atpredetermined positions in the electrode pattern region so as to form aconcave-convex pattern by using the first metal material to form thereflective region pattern 14, wherein the first metal materialpreferably is Al, AlNd, Mo and so on;

In the present embodiment, the storage capacitance bottom electrode maybe a common electrode line (Cst on common) to provide a constant voltageto the common electrode, or may be a portion of the gate line (Cst onGate).

Step 2: forming the gate insulation layer 3, and forming a semiconductorisland by using a semiconductor material to form the active layer 4,wherein the semiconductor material preferably is a-Si, p-Si, IGZO and soon;

Step 3: forming the data line, the source electrode 5 and the drainelectrode 6 by using a second metal material, and remaining a portion ofthe second metal material on the gate insulation layer 3 correspondingto the reflective region pattern 14 to form the reflective region metalelectrode layer 15, which is used to achieve the function of areflective layer, wherein the second metal material preferably is Al,AlNd, Mo and so on;

Steps 4˜6: depositing a red resin layer R and performing a patterningprocess, and depositing a green resin layer G and a blue resin layer Band performing patterning processes in a manner similar to the red resinlayer, so as to form the color resin layer 11;

Step 7: forming the pixel electrode 7 connected with the drain electrode6 by using a transparent conductive material, wherein the transparentconductive material preferably is ITO, IZO and the like;

Step 8: forming the passivation layer 9 by using an inorganic insulationmaterial, wherein the inorganic insulation material preferably is SiNx,SiOx and the like;

Step 9: forming the common electrode 8 by using a transparent conductivematerial, wherein the common electrode 8 is connected with the storagecapacitance bottom electrode by the via hole (not shown), and thetransparent conductive material preferably is ITO, IZO and the like;

Further, the black matrix layer may be subsequently formed on the thinfilm transistor region on the resultant array substrate by using anopaque resin layer.

It may be understood by those skilled in the art that the pixelelectrode may be of a plate shape or a slit shape, and correspondingly,the common electrode may be a slit shape or a plate shape. The stackorder of the pixel electrode and the common electrode may be reversed,however, the upper electrode must be of a slit shape, and the lowerelectrode must be of a plate-shape.

The embodiments of the invention also provide a display device, whichcomprises the array substrate according to the above embodiments. Thedisplay device may be any products or components having displayfunction, such as a liquid crystal panel, an electronic paper, an OLEDpanel, a liquid crystal TV, a liquid crystal display, a digital photoframe, a cellar phone, a flat panel computer and so on.

The foregoing are only preferable embodiments of the invention. It is tobe noted that, those with ordinary skills in the art may make variousmodifications and changes without departing the technical principle ofthe invention, and these modifications and changes should be deemed tobe within the protection scope of the invention.

1. An array substrate, comprising a gate line and a data line whichdefine a pixel region, wherein the pixel region comprises a thin filmtransistor region and an electrode pattern region, a gate electrode, agate insulation layer, an active layer, a source electrode, a drainelectrode and a passivation layer are formed in the thin film transistorregion, the gate insulation layer, a pixel electrode, the passivationlayer and a common electrode are formed in the electrode pattern region,and the common electrode and the pixel electrode are used for forming amulti-dimensional electric field; and wherein a color resin layer isformed between the gate insulation layer and the pixel electrode.
 2. Thearray substrate according to claim 1, wherein the electrode patternregion further comprises a reflective region and a transmissive region,a reflective region pattern formed of a metal material for the gateelectrode is disposed at a position corresponding to the reflectiveregion of the electrode pattern region on the substrate, the gateinsulation layer is formed on the reflective region pattern; and areflective region metal electrode layer formed of a metal material forthe source and drain electrodes is disposed at a position correspondingto the reflective region pattern on the gate insulation layer.
 3. Thearray substrate according to claim 1, wherein a storage capacitancebottom electrode formed of a metal material for the gate electrode isdisposed in the electrode pattern region, an insulation layer via holeis formed above the storage capacitance bottom electrode, and the commonelectrode is connected with the storage capacitance bottom electrode bythe insulation layer via hole.
 4. The array substrate according to claim1, wherein a protection layer formed of an insulation material isfurther formed on the source electrode, the drain electrode and the gateinsulation layer, and a black matrix layer is formed at a positioncorresponding to the thin film transistor region on the protectionlayer.
 5. A method of manufacturing an array substrate, comprisingprocesses of forming a pixel region, wherein the pixel region comprisesa thin film transistor region and an electrode pattern region, a gateelectrode, a gate insulation layer, an active layer, a source electrode,a drain electrode and a passivation layer are formed in the thin filmtransistor region, the gate insulation layer, a pixel electrode, thepassivation layer and a common electrode are formed in the electrodepattern region, and the common electrode and the pixel electrode areused for forming a multi-dimensional electric field; wherein afterforming the gate insulation layer and before forming the pixelelectrode, a color resin layer is formed above the gate insulationlayer.
 6. The method of manufacturing the array substrate according toclaim 5, wherein the electrode pattern region further comprises areflective region and a transmissive region, in a process of forming thegate electrode, a reflective region pattern formed of a metal materialfor the gate electrode is disposed at a position corresponding to thereflective region of the electrode pattern region on the substrate; andin a process of forming the source and the drain electrodes, areflective region metal electrode layer formed of a metal material forthe source and drain electrodes is disposed at a position correspondingto the reflective region pattern on the gate insulation layer.
 7. Themethod of manufacturing the array substrate according to claim 5,wherein in a process of forming the gate electrode, a storagecapacitance bottom electrode formed of a metal material for the gateelectrode is disposed in the electrode pattern region; and an insulationlayer via hole is formed above the storage capacitance bottom electrodebefore forming the common electrode, so that the common electrode isconnected with the storage capacitance bottom electrode by theinsulation layer via hole.
 8. The method of manufacturing the arraysubstrate according to claim 5, wherein a protection layer formed of aninsulation material is formed after forming the source and drainelectrodes, and a black matrix layer is formed at a positioncorresponding to the thin film transistor region on the protectionlayer.
 9. A display device, comprising the array substrate according toclaim
 1. 10. The display device according to claim 9, wherein theelectrode pattern region further comprises a reflective region and atransmissive region, a reflective region pattern formed of a metalmaterial for the gate electrode is disposed at a position correspondingto the reflective region of the electrode pattern region on thesubstrate, the gate insulation layer is formed on the reflective regionpattern; and a reflective region metal electrode layer formed of a metalmaterial for the source and drain electrodes is disposed at a positioncorresponding to the reflective region pattern on the gate insulationlayer.
 11. The display device according to claim 9, wherein a storagecapacitance bottom electrode formed of a metal material for the gateelectrode is disposed in the electrode pattern region, an insulationlayer via hole is formed above the storage capacitance bottom electrode,and the common electrode is connected with the storage capacitancebottom electrode by the insulation layer via hole.
 12. The displaydevice according to claim 9, wherein a protection layer formed of aninsulation material is further formed on the source electrode, the drainelectrode and the gate insulation layer, and a black matrix layer isformed at a position corresponding to the thin film transistor region onthe protection layer.